Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The a type structural decomposition method. Its main goal reducing number look-up table (LUT) elements FSM compared three-block circuit. idea using codes collections outputs for replacing inputs and variables. interstate transitions are defined generated two adjacent cycles synchronization. One, output collection codes, kept into register. To optimize block-generating outputs, new proposed. encoded as an element some class states. This approach allows both logic levels inter-level interconnections LUT-based circuit be diminished. An example with applied shown. Moreover, results our research represented. was conducted CAD tool Vivado by Xilinx. experiments prove that reduction such known methods Auto One-hot Vivado, JEDI. gives better than based on simultaneous replacement encoding outputs. Compared FSMs, LUT counts reduced average 10.07% without significant value operating frequency. gain increases increasing numbers states inputs.